Power semiconductor devices should provide the minimum possible turn-on resistance, reverse leakage current and high switching speed at the rated breakdown voltage, to reduce the operational conduction loss and switching loss. The wide bandgap (Eg=3.26 eV), high threshold field of dielectric breakdown (2.2 MV/cm) and high thermal conductivity (4.9 W/cm-K) of silicon carbide (SiC) make it an ideal material for power switching devices. The thickness of voltage supporting layer (a low doping concentration drift layer) of power devices made of SiC is one-tenth of that made of silicon at the same rated blocking voltage, and the theoretical conduction resistance of SiC power devices can be hundreds times lower than Si power devices.
However, the wide bandgap of SiC also makes the turn-on voltage of body diode of SiC metal oxide semiconductor field effect transistor (MOSFET) reach to nearly 3V, which will result in a larger loss during switching and limit the switching speed. Furthermore, the basal plane dislocations in SiC drift layer will expand into stacking faults due to recombination of carriers during the forward conducting of body diode. SiC MOSFET may degrade or even fail due to these stacking faults. Therefore, a SiC MOSFET sometimes co-packages an anti-parallelly connected SiC Schottky diode externally to increase the operating speed, reduce switching loss and avoid reliability issues brought by stacking faults.
The U.S. Pat. No. 9,209,293 provides an integrated device, in which junction barrier Schottky (JBS) diodes are embedded in a metal oxide semiconductor (MOS) field-effect transistor cell array. The integrated device includes a plurality of areas, each area comprising: a plurality of MOS transistor cells, wherein any two adjacent MOS transistor cells are separated by a separating line, and wherein a first MOS transistor cell and a second MOS transistor cell are adjacent in a first direction and separated by a first separating line, and the first MOS transistor cell and a third MOS transistor cell are adjacent in a second direction and separated by a second separating line, wherein the MOS transistor cells of each area comprises a plurality of well regions of a second conductivity type, and any two adjacent well regions are separated by one of the separation lines; a drift layer of the first conductivity type, disposed on a substrate, wherein the well regions are disposed in the drift layer; at least one JBS diode, disposed in the drift layer at an intersection region between the first separating line and the second separating line, wherein the JBS diode is connected in anti-parallel to the first, second and third MOS transistor cells, wherein the at least one JBS diode comprises a plurality of first junction barrier regions of the second conductivity, disposed in the middle of the drift layer of the intersection region and the plurality of first junction barrier regions extend into corners of the well regions; a plurality pf source regions of a first conductivity, disposed in the middle of the well regions; a plurality of body regions of the second conductivity type, disposed in the middle of the source regions in the well regions; a plurality of source contacts, disposed on and electrically connected to the body regions and a portion of the source regions; a first anode contact, covering a portion of the first junction barrier regions and a portion of the drift layer and electrically connected to the source contacts and the first junction barrier regions; and a cathode, disposed in the substrate below the drift layer.
Also as the U.S. Pat. No. 6,979,863, in addition to the metal oxide semiconductor field-effect transistor cells, it allocates extra areas to form junction barrier Schottky diodes in an anti-parallel connection.
In the above-identified techniques, the JBS diodes provided in the U.S. Pat. No. 9,209,293 are disposed in the intersection regions between the two adjacent MOS transistor cells. In other words, the JBS diodes occupy the area of a portion of the well regions and a portion of the separating lines respectively. In this way, the channel width (Wch, in the unit of μm) of one MOS transistor cell will be reduced. On the other hand, the U.S. Pat. No. 6,979,863 an additional chip area is required to be allocated for the JBS diode, and there is no transistor channel in the portion of that chip area. Both of the two disclosures will reduce the total channel width per unit area (μm/cm2) of the chip, resulting in a decrease of the transistor current density flowing through the integrated device and an increase of the transistor specific on-resistance (the product of the transistor on-resistance and chip area, in the unit of mΩ·cm2).